1. Field of Invention
The present invention relates to an integrated circuit and a method of fabricating the same. More particularly, the present invention relates to a semiconductor device and a method of fabricating the same.
2. Description of Related Art
In common semiconductor processes, after a metal oxide semiconductor (MOS) transistor is fabricated, a stress layer will be formed on the substrate to increase the mobility of electrons or holes in the channel of the MOS transistor. In semiconductor processes with a line width lower than 65 nm, for a p-type MOS transistor, a stress layer having compressive stress can be formed on the substrate, so as to generate the compressive stress along the channel direction in the p-type MOS transistor; and for an n-type MOS transistor, a stress layer having tensile stress can be formed on the substrate, so as to generate the tensile stress along the channel direction of the n-type transistor. With the increase of the compressive stress or the tensile stress, the mobility of holes or electrons in the channel is also increased, so as to increase the drive current, and further improve the performance of the device.
However, with the development of semiconductor technology, the requirements on the performance of semiconductor devices are gradually becoming higher and higher. Therefore, it is an important and urgent task to further increase the compressive stress or the tensile stress along the channel direction in the MOS transistor, so as to improve the mobility of electrons or holes in the channel.
FIGS. 6A˜6B are sectional flow charts of a method of fabricating a semiconductor device to improve the mobility of electrons or holes in the channel according to prior art.
Referring to FIG. 6A, a MOS transistor 20 is formed on a substrate 10, and metal silicide layers 22 and 24 are formed on the gate structure 13 and source/drain region 18, respectively. Referring to FIG. 6B, to enable the stress layer formed subsequently to have better stress performance, normally an etching process is performed before the stress layer is formed, so as to reduce the width S1 of the spacer 14 to S2, which allows the stress layer formed subsequently to be closer to the channel, thus the mobility of electrons or holes in the channel is increased. However, when the etching process is performed, the metal silicide layers 22 and 24 are directly exposed to the etching environment without any protection, the metal silicide layers 22 and 24 will be damaged after the etching process, especially after the over etching, resulting in unsatisfactory sheet resistance.